The invention relates to the configuration of the direct memory access transfer mode of motherboards or host computers, and more particularly to a process of configuring a motherboard receiving attachment to device(s), such as peripheral storage, in accordance with the particular cable being employed for the attachment of the device(s) to the motherboard.
The AT Attachment (ATA) storage interface has become very popular on most personal computers. It provides attachment between a host and storage systems for systems manufacturers, software suppliers and system integrators. The storage systems may be for instance disk drives or CDROM drives or any device or storage peripheral being placed on the interface.
FIGS. 1A to 1C illustrate the interface cabling diagram of a host computer, or more simply a motherboard 3, with one or two devices which are connected in a daisy chain configuration. FIG. 1A illustrates the attachment of two devices, a device 1 which is configured in a master mode, and a device 2 which operates as a slave. The attachment is achieved by means of AT Attachment cable 4, for instance the popular 40-connector attachment cable, also known under the designation Integrated Drive Electronics or IDE. FIGS. 1B and 1C show more particularly the attachment of one unique device to the Motherboard by means of IDE cable 4 which, in this case, operates as a master device.
The AT Attachment interface has been subject a strong effort of standardization in order to increase speed, to improve interchangeability and to bring additional functions. Most of the recommendations and regulations which have been developed in this particular technical area can be found in the publications of the Technical Committee T13 for the National Committee on Information Technology Standards (NCITS), which is accredited and operates under the rules approved by the American National Standards Institute (A.N.S.I.)
Recent developments brought to the AT Attachment interface have been formulated in the ATA-3/ATA-4 specification which define the connectors and cables for physical interconnection between the host and the devices, as well as the electrical/logical characteristics of the interconnecting signals, the commands and protocols involved in the operation of the storage device. These developments particularly recommend the replacement of the traditional 40-conductor cable by a 80-conductor cablexe2x80x94known as an Ultra-ATRA 66 cablexe2x80x94in order to improve signal quality for data transfer modes that do not require a 80-conductor cable assembly. In the near future, the popular 40-conductor IDE cable is thus expected to be superseded by the Ultra-ATA 66 cable.
Ultra-ATA cable has 80 conductors with every two conductors having one conductor being connected to the ground in order to improve the quality of the signal which is conveyed via the cable. Because of the improvement brought to the quality of the signal, the 80-conductor cable is capable of conveying higher speeds without data corruption. Ultra-ATA cable is required for Ultra-DMA modes which are greater than mode 2 (33 Megabytes per second) and is recommended for Ultra-DMA. The commands and protocols which are involved in this Ultra-ATA 66 cable are specified in the ATA-4 standards as well as in the T13 document xe2x80x9cd98133, New timing for Ultra DMAxe2x80x9d
A motherboard which supports the Ultra-ATA/66 is capable of operating at different modes and speeds, the Ultra-ATA/66 mode but also the lower modes. Since both 40-conductor cables and 80-conductor cables share the same physical connector, it is highly desirable to give the possibility to the processor located on the motherboard to determine which physical cable is being present for the attachment of the peripheral storage(s). Indeed, should the motherboard be configured to operate at 66 megabytes per second via a traditional IDE cable, it is most likely that data corruption might occur. Therefore ATA4 specification recommends that a cable detection circuit be implemented in order to reliably determine the presence of the 80-conductor cable for the attachment of storage devices to the motherboard, before allowing higher speeds and higher modes. Document 1153D xe2x80x9cAT Attachment with Packet Interface Extension (ATA/ATAPI-4)xe2x80x9d, published as ANSI NCITS 317-1998 and available from ANSI, 11 West 42nd Street, New York, N.Y. 10036, as well as document xe2x80x9cProposal for Ultra ATA/66xe2x80x9d, referenced T13/D98133, revision 1 of the T13 Committee, address this particular problem of 80-conductor cable detection.
The method which is proposed in these prior art documents is based on the use of a particular pin of the AT attachment interface, pin-34 which is also used for the Passed_on_diagnostics (PDIAG#) signal. Normally, the PDIAG# signal is involved in the communication between the master device 1 and the slave device 2 after the execution of the diagnostic tests in the latter. More specifically, as soon as the slave device has passed its diagnostic tests after power-on reset, the latter is expected to issue an electrical low level on the PDIAG# pin in order to inform the master device of the correct execution and completion of the diagnostic procedure. Any device which complies with ATA-3 or subsequent standards is expected, then, to release the PDIAG# pin no later than after the first command following a power on or hardware reset sequence.
In the Standards ATA-4, the cable detection is based on a special arrangement which is brought to the 80-conductor cable in order to achieve the cable detection. Indeed, in the 80-conductor cable, the pin-34, which normally carries the PDIAG# signal in the usual 40-conductor cable, is isolated between the host connector and the devices connectors. Therefore, the PDIAG# signal can no longer be transmitted to the pin-34 on the host side. On the host side the pin 34 (PGIAG#) is grounded in the enclosure of the connector and a pull-up resistance is provided on this pin on the motherboard.
The prior art method of ATA-4 specifications involves, during the Power-On Self Tests (POST), a determination of the electrical status of the pin 34 on the motherboard, which is performed after the release by the devices of the pin-34 which, as evoked above, is normally expected no later than after the first command received by the device. An alternative method is also known to take advantage of pin-34 in the cable detection process. This involves the use of a capacitor which is connected between the ground and the host connector. The device enters into a detecting step where it tries to detect the charging of the capacity which, of course, can not be detected if a 80-cable is present since pin-34 of the motherboard is isolated from Pin-34 of the devices. Such alternative is particularly addressed in document xe2x80x9cProposal for Ultra ATA/66xe2x80x9d, referenced T13/D98133, revision 1 of the T13 Committee
The methods which are summarized above remain effective as long as the slave device shows a behavior which is that being expected, that is to say it releases the PDIAG# pin after the first command received during the first IDE transaction with the board. However, should the device behave slightly differentlyxe2x80x94which is the case for many CDROM devicesxe2x80x94and not strictly conform to the ATA-3 specifications, the result might be a corruption of data. Indeed, if, for one reason, a CDROM slave device, for instance, does not release the pin-34 after the first command being received from the motherboard, then the motherboard will find that pin-34 carries a low level, which results from the incorrect behavior of the slave device, and not from the internal ground wiring of pin 34 of a potential 80-conductor cable being plugged in the connector. Therefore, in this case, the processor under control of the bios would make an incorrect interpretation of the low state of pin-34, and will see in the low state the evidence of the presence of a 80-conductor cable which is not present. In this situation, since the processor and the BIOS would allow higher Ultra-DMA rates, data corruption would inevitably occur.
It is therefore desirable to prevent any data corruption by enhancing the cable detection methods which are known in the art, and particularly those disclosed in the T13/D98133 and ATA-4 standards for the purpose of configuring the Ultra-DMA mode.
It is an object of the present invention to provide an enhanced direct memory access transfer configuring process, applicable for instance for Ultra-DMA configuration, which is based on a detection of the cable being independent on the compliance to the ATA-3 or subsequent standards of a device which is attached to a host or a motherboard.
This object is achieved by the process for configuring a motherboard or host computer which is defined in claim 1. Basically, the process allows to distinguish the use of a first cable of medium quality allowing communication mode at a first speed, with a second high-quality cable allowing communication mode at a second higher speed without data corruption. The high-quality cable comprises a particular conductor which is cut between the motherboard or host computer and the attached devices, and which is also internally connected to one first voltage in the enclosure of the cable. This particular conductor is chosen to correspond to one pin which the attached devices usually release when they receives a reset pulse. On the motherboard, the particular pin is pulled-up to a second voltage. The cable detection and the speed configuration is based upon the sampling, on the motherboard, of the electrical voltage of that particular terminal when a reset pulse is being transmitted to the devices via the cable. The process is then made aware of the particular type of cable which is used, and can automatically configure the speed of the communication mode in order to prevent data corruption.
The discrimination between a n-conductor medium quality cable and a n-conductor high quality cable can be achieved.
However, the invention is particularly useful in the context of the Ultra-ATA (Ultra-DMA) 80-connector cable detection and mode configuration. In this context, the particular conductor is chosen to be the 34th conductor which carries the Passed on Diagnostic (PDIAG#) signal and the invention then permits to distinguish the popular IDE 40-conductor cable from the Ultra-ATA 80-conductor allowing Ultra-DMA mode of type greater than 2 without data corruption. The right cable detection and Ultra-DMA mode configuration is made possible, even if the attached devices do not release the PDIAG# pin after the first command, contrary to the known methods.
In a first embodiment of the invention, the sampling of the PDIAG# terminal (pin 34) is performed during the power-on by means of a sampling circuit operational during the main reset procedure of the machine, and which can sample the electrical state of the PDIAG# pin during the reset pulse. After the sampling, as soon as the processing means takes the control of the motherboard, the sampled value can be read in order to achieve the Ultra-DMA mode configuration.
In a second embodiment of the invention, the state of the PDIAG# pin is read, during a second reset occurring after the main reset procedure, and which is issued by the processor on the mother-board. During this second reset pulse which is transmitted to the devices which are connected to the ATA cable, the processing means controls the sampling of the pin-34 and the transfer of its value into a register which it may read before allowing high Ultra-DMA transfer modes. This sampling can be achieved by means of a General Purpose Input element (GPI) which is available on the motherboard.
Preferably, the reset control signal is provided by means of hardware under control of the processor, for instance with a general purpose output element (GPO) providing a reset pulse which can be transmitted via the cable to the device.
Alternatively, in a third embodiment, the reset control signal is provided into a software command under control of said processor and which is transmitted to the devices via an IDE transaction. The value read on pin-34 can be again stored into a gpi device.
A substantial advantage of this third embodiment results from the fact that minor hardware changes are required in order to embody the invention into an existing motherboard. In the case where the motherboard is already fitted with a general purpose input element which is connected to pin 34, then Ultra-ATA mode configuration is rendered possible without need for hardware changes.
In addition to a configuration process, the invention also provides with a motherboard which is fitted with automatic communication mode configuration, such as Ultra-DMA for instance. The motherboard comprises at least one host connector for receiving attachment to at least one device or peripheral storage. The attachment is made by either a first cable of medium quality for operation at said first speed or a second cable of higher-quality for operation at a second higher speed. The high-quality cable has one particular conductor which is chosen so as to correspond to a pin which is released by the attached devices when the latter are receiving a reset pulse.
The particular conductor is cut between the host connector and the device connector and the corresponding terminal on the host side is internally wired to a first voltage, for instance the ground voltage. A pull-up resistance is used to connect the terminal to a second voltage, for instance the supply voltage. The motherboard includes means for sampling the logical state of the terminal on the host connector when a reset pulse is being transmitted to the attached device(s) in order to determine the actual cable which is plugged and configure the Ultra-DMA mode accordingly.
At last, the invention provides a process for validating the assembling of an Information Handling System (IHS) comprising a motherboard (3) dedicated to communicate with at least one device or peripheral storage which is potentially attached via a cable. The motherboard comprises processing and storage means, and at least one host connector for receiving attachment to said at least one device or peripheral storage. The attachment can be performed by a first cable of medium quality allowing the first speed communication which has one particular conductor which is released by the device or peripheral storage upon reception of a reset pulse. Conversely, the attachment can be achieved by a high-quality cable which has the particular conductor which is cut and the corresponding terminal located on the host side is internally wired in the enclosure of said high-quality cable in order to received a first voltage. On the motherboard, the particular terminal is pulled-up on the motherboard to a second voltage. The validation process involves the sampling of the logical state carried by said particular terminal during a reset pulse generated by the mother board. This pulse is transmitted to the said at least one potentially attached device or peripheral storage and the result of the determination permits to detect the presence of the high quality cable in accordance with the logical state which is sampled. The assembling can thus be validated.